hardware - VHDL: Properly clocking another component with respect to setup -

i working on fpga project in vhdl.

i need copy 16 bit shift register fifo each time fills (eg after 16 new data bits have been fed shift register, want take newly formed 16 bit word , send fifo)

my question is, need set data @ input of fifo 1 clock before asserting clock line on fifo? generic vhdl question, , not specific fifos.

basically, possible set data , toggle clock in same operation, or need basic state machine set data on 1 clock edge , toggle fifo clock on next?

for instance:

fifo_d_in( 7 downto 0 ) <= shift_register; fifo_clk <= '1'; 

or

if( state = 1 )     fifo_d_in( 7 downto 0 ) <= shift_register;     state <= two; elsif( state = 2 )     fifo_clk <= '1'; end if; 

my gut tells me have setup data first, satisfy setup & hold requirements of input registers.

thanks!

the data must present setup time before clock edge, asserting clock @ same time possible data changes may result in unstable behaviour.

one way configure shift register have output asserts after last bit of data has been clocked in. 8 bit shift register, after 8th clock signal asserted. easy way accomplish 3 bit counter, when bits 1 output 1. signal connected clken of fifo on 9th clock edge, data @ output of shift register clocked the fifo. possible clock in next serial bit of data shift register on 9th clock.

       shift reg             fifo        -------------        ---------       -|din   dout |--------| din   |        |      full |--------| clken |      - |>          |      --|>      |      | -------------      | ---------      |                    |  clk ----------------------- 

in above diagram, full asserted instant after last bit of data clocked in fill shift register, , deasserted on next cycle. full can combinatorial logic.