verilog - how can I reduce mux size -
module memory_module (input clk,input[0:6] address,input [0:7]data_input, input read_write,output [0:7] data_output,input enable,output ready); reg ready; reg [0:7] data_output; reg [0:7] memory [127:0]; initial begin ready=0; end @(posedge clk) begin if(enable) begin ready=0; if(read_write) begin data_output[0:3]= memory[address][0:3]; data_output[4:7]= memory[address][4:7]; end else begin memory[address][4:7]=data_input[4:7]; memory[address][0:3]=data_input[0:3]; end ready=1; end else ready=0; end endmodule here simple verilog code memory module design (i want make code more efficient) also when write data_output[0:7]= memory[address][0:7]; creates 8x1 mux by writing