verilog - How to execute a for loop over multiple clock cycles? -

the loop working , happening in single clock cycle. how make run single iteration per cycle?

   `timescale 1ns/10ps     module multiplier (clock,multiplier,multiplicand,start,done,product);      input   [7:0]   multiplier ,multiplicand;     input           start;     input           clock;     output  [15:0]  product;     output          done;      reg     [15:0]  multiplierf ,multiplicandf;     reg     [15:0]  productf;     reg             donef;      integer i;      assign product  =   productf;     assign done     =   donef;      task rpa_16;      input   [15:0]      multiplierf;     inout   [15:0]      productf;      assign productf = multiplierf + productf;      endtask      @ (posedge clock or posedge start)     begin     if(start)         begin             multiplierf     =   0 ;             multiplicandf   =   0 ;             productf        =   0 ;             donef           =   0 ;         end     else         begin             multiplierf     =   {8'b0,multiplier};             multiplicandf    =   {8'b0,multiplicand};           end             end       @(posedge clk)     begin             if(!donef)                 begin                     (i=0;i<7;i=i+1)                         begin                             if(multiplicand[i])                                 begin                                 rpa_16(multiplierf,productf);                                  multiplierf =  multiplierf << 1;                                 productf     = productf;                                                        end                             else                                 begin                                 multiplierf = multiplierf << 1;                                 end                         end                     donef = 1;                 end     end 

i cant paste picture of waveform , want increment after each positive edge . whats happening , loop executes in single clock cycle , output.

for loops not imply sequential in verilog. if want loop takes 8 clock cycles, you'll have rewrite explicit counter variable, perhaps this:

always @(posedge clk or negedge reset_) if(!reset_) begin    multiplierf <= 0;    loopcount   <= 0;    donef       <= 0; end else begin   if(!donef) begin      loopcount <= loopcount + 1;      if(multiplicand[loopcount]) begin        rpa_16(multiplierf,productf);         multiplierf =  multiplierf << 1;        productf    = productf;                             end else begin        multiplierf = multiplierf << 1;      end   end   if(loopcount == 7) donef <= 1; end 

also, should not assigning variables multiplierf in multiple blocks, non-deterministic behavior , fail synthesize. on posedge clk both blocks execute , cannot know 1 execute last, may give different results on different simulators.